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July Webcast & Video: Upgrade Partitioning FPGA Designs for Redundancy and Information Security

announcements@altera.com (Altera Webcast eNewsletter) — Thu, 02 Jul 2009 21:12:00 GMT

July Webcast & Video: Upgrade Partitioning FPGA Designs for Redundancy and Information Security

July 2009

www.altera.com

Partitioning FPGA Designs for Redundancy and Information Security, 20 minutes
Ensure high up-time and reliability for designs requiring fault tolerance, redundancy, or information security. View this webcast to see how the new low power, secure Cyclone^® III LS FPGAs provide design separation for complete functional independence on a single chip

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	Accelerate Your Video Format Conversion Using 1080p Framework, 8 minutes View this video to learn about an easy method for up-conversion, down-conversion, and cross-conversion of SD and HD video streams. You will also learn how a 1080p format conversion reference design provides a flexible, customizable template for fast conversion, right out of the box. View Now

	Innovating with a Full Spectrum of 40-nm FPGAs and ASICs with Transceivers, 12 minutes View this video white paper to see how a full spectrum of FPGAs and ASICs with high-speed transceivers can address your design’s performance requirements. You'll learn about high-speed technology trends, and how Altera’s FPGA and ASIC portfolio enables system architects to meet their design challenges. View Now

	Upgrade Your System’s Resistive Touch Screen to Multi-Touch, 18 minutes Adding multi-touch to a wide variety of products may be easier than you think. View this webcast to learn a very cost effective way to add multi-touch to your system using Altera’s MAX^® II CPLDs and surprisingly simple IP. View Now

	Analyze FPGA Transceiver Interoperability and Signal Integrity, 8 minutes View this video to learn how Altera’s new Transceiver Signal Integrity Development Kit, Stratix^® IV GX Edition, enables a thorough evaluation of the transceiver’s interoperability and SERDES signal integrity. View Now

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ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

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Altera Announces New Cyclone III LS FPGAs

newsroom@altera.com (Altera Newsroom) — Mon, 29 Jun 2009 15:22:00 GMT

Altera Announces New Cyclone III LS FPGAs

San Jose, Calif., June 29, 2009—Expanding its leadership position in low-power solutions, Altera Corporation (NASDAQ: ALTR) today announced a new low-power FPGA family with security features. The new Altera^® Cyclone^® III LS FPGAs offer the highest logic, memory, and DSP density per board area. These devices are the lowest power FPGAs at less than 0.25W of static power for 200K logic elements (LEs). The Cyclone III LS FPGAs, which are shipping now, target power and board-space-sensitive applications in all market segments including military and industrial.

The security features of the Cyclone III LS FPGA include a comprehensive information-assurance design suite that offers anti-tamper, design-security and design-separation capabilities. To protect highly sensitive information, the Cyclone III LS FPGAs' anti-tamper features include JTAG port protection, tamper monitoring, and cyclical redundancy check (CRC). Offering another layer of protection, these devices feature a proven industry-standard AES 256-bit encryption key for design security. Where size, weight, and power (SWaP) requirements are crucial, the design-separation feature of the Cyclone III LS FPGA enables high-assurance and industrial-safety applications in a single chip through logic, routing and I/O bank separation.

"The secret to the Cyclone series’ success has been a strong focus on customer applications, which allows Altera to supply the right mix of low power, high functionality, and small form-factor solutions," said Luanne Schirrmeister, senior director of component product marketing at Altera Corporation. "The introduction of the Cyclone III LS devices extends Altera's low-power leadership and specifically addresses the security needs that are paramount for the military and industrial markets. We're offering a complete solution that protects against IP theft and tampering."

Cyclone III LS FPGAs allow a single-chip solution for next-generation military applications such as software-defined radio (SDR), crypto-subsystems, and crypto modernization equipment where long battery life, density at the lowest power, and small board space are required. The additional security features of the Cyclone III LS FPGAs give designers of secure communications applications the assurance that their information will be protected with anti-tamper technology.

The unique features of the Cyclone III LS FPGA also provide the optimal solution for industrial applications, specifically motion control, Industrial Ethernet, and industrial safety. Using the design-separation feature lowers system power and increases integration while offering design redundancy for safety-critical applications. For detailed information on these new devices, see www.altera.com/pr/cycloneiii.

Availability

Cyclone III LS devices are shipping now. Contact your Altera® sales representative for pricing. All of the Cyclone III LS devices will be supported in the Quartus® II software version 9.0 SP2, see www.altera.com/pr/download.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.

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White Paper: "Protecting the FPGA Design From Common Threats"

newsroom@altera.com (Altera White Papers) — Mon, 29 Jun 2009 15:15:00 GMT

White Paper: "Protecting the FPGA Design From Common Threats"

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White Paper: "Enabling Design Separation for High-Reliability and Information-Assurance Systems"

newsroom@altera.com (Altera White Papers) — Mon, 29 Jun 2009 15:05:00 GMT

White Paper: "Enabling Design Separation for High-Reliability and Information-Assurance Systems"

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White Paper: "Enabling Image Format Conversion in FPGAs"

newsroom@altera.com (Altera White Papers) — Wed, 24 Jun 2009 23:59:00 GMT

White Paper: "Enabling Image Format Conversion in FPGAs"

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June Webcast & Video: Upgrade Your System's Resistive Touch Screen to Multi-Touch

announcements@altera.com (Altera Webcast eNewsletter) — Wed, 03 Jun 2009 18:37:00 GMT

June Webcast & Video: Upgrade Your System's Resistive Touch Screen to Multi-Touch

June 2009

www.altera.com

Upgrade Your System’s Resistive Touch Screen to Multi-Touch,
18 minutes
Adding multi-touch to a wide variety of products may be easier than you think. View this webcast to learn a very cost effective way to add multi-touch to your system using Altera’s MAX^® II CPLDs and surprisingly simple IP.

View Now

	Analyze FPGA Transceiver Interoperability and Signal Integrity, 8 minutes View this video to learn how Altera’s new Transceiver Signal Integrity Development Kit, Stratix^® IV GX Edition, enables a thorough evaluation of the transceiver’s interoperability and SERDES signal integrity. View Now

	WiMAX System Design Using Simulink and Altera’s DSP Builder, 60 minutes In this webcast, you’ll see how you can take advantage of FPGAs’ high DSP performance with DSP Builder. You'll learn to build highly optimized DSP designs within The MathWorks Simulink, as well as watching a WiMAX wireless system design example. View Now

	Tuning High-Speed Serial Links for Optimal Receive and Transmit Equalization, 20 minutes View this webcast to learn how advanced FPGA transceivers address the challenges of lossy backplanes. You'll also learn how silicon features and simulation tools help you find the optimal receive and transmit equalization settings for a high-speed serial link. View Now

	Innovating with a Full Spectrum of 40-nm FPGAs and ASICs with Transceivers, 12 minutes View this video white paper to see how a full spectrum of FPGAs and ASICs with high-speed transceivers can address your design’s performance requirements. You’ll learn about high-speed technology trends, and how Altera’s FPGA and ASIC portfolio enables system architects to meet their design challenges. View Now

Product Announcements & Updates
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Altera Eases Development of 40-nm FPGAs with Stratix IV GX FPGA Development Kit

newsroom@altera.com (Altera Newsroom) — Wed, 03 Jun 2009 14:43:00 GMT

Altera Eases Development of 40-nm FPGAs with Stratix IV GX FPGA Development Kit

San Jose, Calif., June 3, 2009—Altera Corporation (NASDAQ: ALTR) today announced availability of the Stratix^® IV GX FPGA Development Kit. The kit features hardware and software solutions for the rapid creation of designs using Altera's high-performance 40-nm Stratix IV GX FPGAs with integrated 8.5-Gbps transceivers. The development kit provides an ideal environment for designing and testing high-speed serial interfaces, such as PCI Express (PCIe) Gen2, with up to x8-lane configurations.

The Stratix IV GX FPGA Development Kit offers a complete PCIe Gen2 end-point hardware design package, featuring a PCI-SIG-compliant board and two PCIe Gen2 hard intellectual property (IP) cores in the Stratix IV GX FPGA. A PCIe high-performance reference design that demonstrates both the software and hardware elements of a PCIe system is available for download on the Altera^® website. The two elements of this reference design communicate with drivers created using Jungo's PCIe WinDriver tool forming a fully functional PCIe system. Several other popular protocols are supported by the development kit through the use of high-speed mezzanine cards available from Altera partners, including 10 Gigabit Ethernet (10 GbE), CPRI, OBSAI, SAS/SATA and Serial RapidIO^® (SRIO).

“We work closely with Altera to ensure our PCIe WinDriver development toolkit complement and work seamlessly with the PCIe hard IP cores in Stratix IV GX FPGAs," said Ophir Herbst, general manager of Jungo's connectivity business unit. "Our proven software drivers in combination with Altera's Stratix IV GX FPGA Development Kit provide our mutual customers a complete environment to design and implement leading-edge PCIe 2.0 x8 solutions.”

The Stratix IV GX FPGA Development Kit provides customers with industry-leading innovations within Stratix IV GX FPGAs, including 36 full-duplex transceivers (24 of which operate at up to 8.5 Gbps), two PCIe hard IP blocks, 230K logic elements (LEs) and 13.9 Mbits of embedded memory. The development kit features a Stratix IV GX EP4SGX230 FPGA-based development board, a one-year license of Quartus^® II Software, Development Kit Edition and access to Altera's MegaCore^® IP library including the Nios^® II Embedded Design Suite.

Pricing and Availability

The Stratix IV GX FPGA Development Kit currently is available and priced at $4,495. To learn more about this kit, or to purchase, visit www.altera.com/pr/sivgxkit. For more information on Stratix IV FPGAs, contact your local Altera sales representative or visit www.altera.com/pr/stratix4.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.

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Altera Ships Highest Density, Highest System-Bandwidth FPGA Targeting 40G/100G Applications

newsroom@altera.com (Altera Newsroom) — Mon, 01 Jun 2009 16:45:00 GMT

Altera Ships Highest Density, Highest System-Bandwidth FPGA Targeting 40G/100G Applications

San Jose, Calif., June 1, 2009—Altera Corporation (NASDAQ: ALTR) today announced availability of the industry's highest density, highest system-bandwidth FPGA to address the stringent demands of today's bandwidth-heavy applications. Featuring 11.3-Gbps transceivers and 530K logic elements (LEs), the Stratix^® IV GT EP4S40G5 and EP4S100G5 FPGAs are the latest variants of Altera's 40-nm Stratix IV FPGA family shipping to customers. Stratix IV GT FPGAs support next-generation 40G/100G technologies, including 40/100 Gigabit Ethernet (GbE) media access controllers (MACs), optical transport network (OTN) framers and mappers, 40G/100G Enhanced Forward Error Correction (EFEC) solutions, and 10G chip-to-chip and chip-to-module bridging applications used in communications systems, high-end test equipment and military communications systems.

“From a test perspective, building the 100G ecosystem requires reliable functionality from the physical layer upwards. The breadth and depth of 100G applications demands silicon solutions that offer sophisticated and deep functionality, high performance and density,” said Jerry Gentile, senior vice president in JDSU's communications test and measurement business segment. “Supported by Altera's Stratix IV GT FPGAs, JDSU test solutions are ready for the comprehensive testing and validation of high-end communication systems with the ability to scale up to the latest communication solutions.”

Stratix IV GT devices are the only FPGAs that offer a single-chip solution featuring 11.3-Gbps integrated transceivers that can interface directly to a CFP optical module and meet the emerging IEEE 802.3ba standard for 100G MACs. The unprecedented density and bandwidth in Stratix IV GT FPGAs provide designers of 40G/100G applications the flexibility to incorporate traffic management, packet processing and their own custom functionality into a single device.

Stratix IV GT FPGAs deliver breakthrough levels of system bandwidth and power efficiency for high-bandwidth applications. Stratix IV GT devices feature up to 48 integrated transceivers, a low 0.9V core power supply, on-die and on-packing decoupling, 20.7 Mbits of embedded memory, 1,024 18x18 multipliers and up to 530K LEs. The devices support a wide variety of protocols and standards, including SFI-S, SFI-5.1, SFI-5.2, MLD, Interlaken, CEI-6G/11G, CAUI, XLAUI and feature hard IP for PCIe Gen1 and Gen2 (x1, x4, x8).

“The increased usage of broadband content like HDTV and Internet video is placing tremendous strains on older networks that were not designed to manage the amount of traffic these applications generate,“ said Luanne Schirrmeister, senior director of component product marketing, Altera Corporation. “This is forcing the telecommunications industry to ramp up their 40G/100G networks as quickly as possible. With Stratix IV GT FPGAs, we deliver a single-chip solution that is specifically optimized to address the high-speed data-rate and bandwidth requirements of this emerging market.”

Stratix IV GT FPGA Availability

The Stratix IV GT EP4S40G5 and EP4S100G5 devices are currently shipping, with other family members scheduled to ship in 2009. For more information on Stratix IV GT FPGAs and how the devices can support 40G/100G applications, contact your local Altera sales representative or visit http://www.altera.com/pr/stratixIV-transceivers. To view a white paper that highlights how Altera's FPGAs enable 40G/100G applications, visit http://www.altera.com/pr/40-100G-wp.

About Altera

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This press release contains a forward-looking statement regarding anticipated shipment of Altera devices in 2009 that is made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that all forward-looking statements involve risks and uncertainty, including without limitation the risk that future performance is dependent on the company’s and third parties’ development technology and manufacture capabilities. Please refer to the company’s Securities and Exchange Commission filings, copies of which are available from the company without charge.

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Altera Ships Arria II GX FPGAs: High-Performance, Low-Cost Transceiver FPGAs for 3-Gbps Applications

newsroom@altera.com (Altera Newsroom) — Mon, 18 May 2009 17:09:00 GMT

Altera Ships Arria II GX FPGAs: High-Performance, Low-Cost Transceiver FPGAs for 3-Gbps Applications

San Jose, Calif., May 18, 2009—Delivering a unique low-power, low-cost and high-performance FPGA solution for 3-Gbps applications, Altera Corporation (NASDAQ: ALTR) today announced it has started shipping Arria^® II GX devices, its third family of 40-nm FPGAs. The Arria II GX family with integrated transceivers joins Stratix^® IV GX and Stratix IV GT FPGAs and HardCopy^®IV GX ASICs to extend the industry' broadest portfolio of transceiver FPGA and ASIC solutions.

Arria II GX FPGAs are the ideal devices for 3-Gbps transceiver applications requiring low-cost FPGAs with high-end capabilities. They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power, compared to competitive high-end FPGAs. Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCI Express (PCIe) and Gigabit Ethernet (GbE). The devices have up to 16 3.75-Gbps transceivers, 256K logic elements (LEs) and 8.5 Mbits of internal RAM. In addition, the Arria II GX FPGAs also support targeted protocols such as CPRI, GPON, XAUI and triple-speed SDI.

“The trend towards high-speed serial interfaces is being driven by our increasing demand for information across varied markets and the designers need for higher bandwidth at lower cost and lower power. The Arria II GX FPGAs with integrated programmable transceivers offer best-in-class signal integrity that provides the flexibility to accelerate product development, while consuming less power than competing solutions,” said Luanne Schirrmeister senior director of component product marketing at Altera Corporation.

The low power of Arria II GX FPGAs reduces the cost of thermal management in end equipment by decreasing the number of fans and heatsinks required compared to competing high-end devices. This enables customers to use programmable logic in thermally constrained environments such as smaller enclosures with limited cooling options. Additionally, the low cost of Arria II GX devices enables system designers to utilize industry-leading programmable logic and transceiver technology in their product designs, allowing product differentiation with customized hardware and increased integration.

Arria II GX FPGAs offer a high-speed logic fabric based on Altera's advanced logic module (ALM) architecture—the same as in Stratix IV FPGAs—making them faster than competing high-performance FPGAs. They also offer higher memory- and multiplier-to-logic ratios than competing low-cost FPGAs. These additional memory and multiplier resources are especially important to 3-Gbps applications in the wireless, wireline, broadcast and military markets that utilize high-speed digital signal processing (DSP) and data processing operations.

Arria II GX devices are supported in Quartus^® II design software version 9.0. In addition, Altera is making available three reference designs, a development kit and four design examples to accelerate the development of solutions using Arria II GX FPGAs. For detailed information on these new devices, seewww.altera.com/pr/arriaiigxship.

Pricing and Availability

The Arria II GX EP2AGX125 device is shipping now, with production devices scheduled for the fourth quarter of this year. Pricing for the smallest Arria II GX device, the EP2AGX20, starts as low as $15 for 100K unit quantities in 2010, which is up to 50 percent lower price than competing high-performance FPGAs. Contact your Altera sales representative for pricing.

About Altera

Altera^® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.

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Altera's Stratix III FPGAs Chosen for Harmonic's Next-Generation Universal Broadcast Video Encoder

announcements@altera.com (Altera) — Mon, 20 Apr 2009 21:57:00 GMT

Altera's Stratix III FPGAs Chosen for Harmonic's Next-Generation Universal Broadcast Video Encoder

San Jose, Calif., April 20, 2009—Altera Corporation (NASDAQ: ALTR) today announced that Harmonic has chosen its Stratix^® III FPGAs for its next-generation high-definition (HD) H.264 1080p video broadcast encoder. Delivering the right combination of performance, programmability, flexibility and low power consumption, the Stratix III devices help Harmonic to improve video quality while consuming significantly less bandwidth.

Altera^® Stratix III devices are used in Harmonic's DiviCom Electra 8000, the world's first encoding and transcoding platform to support MPEG-4 AVC (H.264) and MPEG-2 CODECs in standard-definition (SD) and HD formats up to full frame-rate 1080p 50/60. While helping to provide superior picture quality, Altera's Stratix III devices also contribute to the Electra 8000&'s ground-breaking energy efficiency.

“Harmonic's DiviCom Electra 8000 sets the benchmark for real-time video-processing technology,” said Nimrod Ben-Natan, Vice President of Product Marketing, Solutions and Strategy for Harmonic Inc. “Altera's Stratix III FPGAs help us enhance our video algorithms. Altera offers clear FPGA leadership in digital signal processing (DSP) and external memory performance, while still delivering low power requirements.”

“Altera has made significant investments in our FPGA architecture and solutions to meet the demanding requirements of 1080p video-processing applications,” said Arun Iyengar, senior director of Altera's broadcast and communications business units. “Altera's Stratix III FPGAs deliver twice the video-processing capability of previous-generation FPGAs while maintaining a constant power budget. This allows broadcast leaders like Harmonic to further differentiate its products.”

About Stratix III FPGAs

Altera's Stratix III FPGAs are the industry's lowest power, high-performance 65-nm FPGAs. Stratix III FPGA variants that are logic rich (L) or enhanced (E) for memory and digital signal processing (DSP) allow designers to balance resource requirements without having to design a device any bigger than absolutely necessary, thus saving board real estate, power, compilation time and money. Stratix III FPGAs target high-end core system-processing designs in many applications. For more information on Stratix III FPGAs, visit www.altera.com/pr/stratix3.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices atwww.altera.com. To subscribe to Altera's RSS/XML news feeds, visit Altera RSS Feeds.

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Altera Delivers Stratix IV GX Transceiver Signal Integrity Development Kit

announcements@altera.com (Altera) — Mon, 20 Apr 2009 21:53:00 GMT

Altera Delivers Stratix IV GX Transceiver Signal Integrity Development Kit

San Jose, Calif., April 21, 2009—Altera Corporation (NASDAQ: ALTR) today announced the availability of the Transceiver Signal Integrity Development Kit, Stratix^® IV GX Edition. This full-featured hardware development platform has an Altera^® Stratix IV GX FPGA with transceivers that operate up to 8.5 Gbps, allowing engineers to prototype and test their high-speed interfaces quickly and easily. By utilizing this kit, customers can test drive Altera's new 40-nm Stratix IV GX FPGA under their specific design system requirements.

Signal integrity is a critical design requirement for bandwidth-intensive applications such as digital video and 4G wireless. Altera's FPGAs have a strong track record of superior signal integrity, and this new kit allows users to evaluate transceiver performance for jitter, protocol compliance, and equalization at up to 8.5 Gbps through a simple-to-use graphical user interface (GUI).

The Transceiver Signal Integrity Development Kit, Stratix IV GX Edition includes:

Stratix IV GX Signal Integrity Development Board:

EP4SGX230KF40C3N or EP4SGX230KF40C2N on-board FPGA
8 transceiver channels routed to SMA connectors
Flash memory for storing FPGA images
Embedded USB-Blaster™ for FPGA configuration and control
Power measurement circuitry

Application GUI:

Allows users to change transceiver settings and data patterns
Displays bit error rates for each transceiver channel
Displays temperature and power-consumption information

“The release of our Stratix IV GX signal integrity kit is another successful milestone in Altera's deployment of the industry's first 40-nm FPGAs,” said Luanne Schirrmeister, senior director of component product marketing, Altera. “Over the coming months, Altera will deliver even more 40-nm devices and development kits that will continue to drive the evolution of next-generation markets, such as video over IP, 4G wireless and digital TV.”

Availability

The Transceiver Signal Integrity Development Kit, Stratix IV GX Edition is currently available and is priced at $2,495 for the 4SGX230N/C3 kit and $2,995 for the 4SGX230N/C2 kit. To learn more about this kit, or to place and order, visit www.altera.com/pr/sikit.

About Altera

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