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Altera Increases Productivity for High-Performance DSP Designs by an Order of Magnitude

announcements@altera.com (Altera DSP eNewsletter) — Mon, 30 Jun 2008 15:54:00 GMT

Altera Increases Productivity for High-Performance DSP Designs by an Order of Magnitude

San Jose, Calif., June 30, 2008—Targeting high-performance digital signal processing (DSP) designs, Altera Corporation (NASDAQ: ALTR) today announced its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. This technology allows DSP designers for the first time to automatically generate timing-optimized RTL code based on high-level Simulink design descriptions. With this new DSP Builder feature, designers can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code.

“DSP Builder’s second-generation model-based synthesis technology allows customers to use Simulink as the modeling, simulation and implementation environment of choice for high-performance DSP designs,” said Ken Karnofsky, marketing director for signal processing and communications at The MathWorks. “This technology allows designers to vastly improve their productivity as they implement DSP functionality on Altera’s FPGAs.”

Designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless basestations, the new DSP Builder second-generation synthesis technology delivers dramatic productivity gains. The DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This greatly enhances productivity and enables users to perform system level design exploration rapidly, and to easily scale their design for varying carrier bandwidths, number of carriers, antennas, and sectors. DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.

“Altera continues to set the standard for FPGA design productivity, including high-performance DSP designs,” said Chris Balough, marketing director for software, embedded, and DSP at Altera. “The innovative synthesis technology included in DSP Builder version 8.0 delivers a timing-driven FPGA implementation environment that allows designers to get the system performance they require with the push of a button—enabling an order-of-magnitude productivity gain.”

Availability

Used with Altera’s Quartus^® II design software, DSP Builder version 8.0 is available now for purchase. More information about Altera^® DSP solutions and its DSP Builder tool is available at www.altera.com/dsp. Simulink is available today from The MathWorks at www.mathworks.com.

About DSP Builder

DSP Builder is the leading synthesis technology for implementing Simulink designs in a high-performance FPGA platform quickly and effortlessly. Altera’s DSP Builder reads Simulink model files (.mdl) that are built using DSP Builder/MegaCore^® blocks and generates VHDL files and tool command language (Tcl) scripts for synthesis, hardware implementation and simulation. This technology shortens DSP design cycles by creating the hardware representation of a DSP design in an algorithm-friendly development environment.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.

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Embedded eNewsletter Q2 Issue: Download New Nios II and Quartus II v8.0 Software

announcements@altera.com (Altera Embedded eNewsletter) — Wed, 25 Jun 2008 20:44:00 GMT

Embedded eNewsletter Q2 Issue: Download New Nios II and Quartus II v8.0 Software

Q2 2008

www.altera.com

	Quarterly Spotlight Download New Nios II and Quartus II v8.0 Software Get the latest release of the Nios^® II Embedded Design Suite (EDS) and Quartus^® II software v8.0 today. This latest release includes several improvements including support for 40-nm Stratix^® IV FPGAs and HardCopy^® IV ASICs, an MMU and MPU for the Nios II processor, and Nios II Studio beta-a new software development environment for the Nios II processor that enables faster software compile times. With this software release, you can, for the first time, immediately design with the SLS Corp. USB 2.0 device controller core in the SOPC Builder environment. See what's new with the Nios II EDS and Quartus II software, and download the new versions today.
	Embedded Software & Tools Get a uCLinux BSP for the Nios II Processor from SLS SLS Corp. offers a free evaluation of their uCLinux BSP targeted for the Nios II Embedded Evaluation Kit. The uCLinux BSP will include SLS's Touch Panel LCD Controller IP, Ethernet 10/100 IP, PS/2 IP, SD card controller IP, and VGA IP (source or object). This package will get you started quickly on your uCLinux-based design. Download a free evaluation of this BSP and its related documentation and evaluation IP from SLS. New Graphic Demos from Imagem Technologies for the Nios II Evaluation Kit Download the latest demos for your Nios II Evaluation Kit that showcase the graphic performance of Imagem Technologies ATHLET IP. Tutorials, demos, and a free software evaluation kit are available from Imagem Technologies. Literature & Technical Resources Inspiration for Embedded Designs: Award-Winning White Papers Check out the top 19 white papers of the latest Nios^® II Embedded Processor Design Contest, with finalists selected from over 700 entries. See how you can use Nios II processors in applications such as motion control, networking, and signal, data, and image processing. Winning papers include: Nios II Processor Based Camera Design Smart Self-Controlled Vehicle for Motion Image Tracking RTOS Acceleration Using Instruction Set Customization Intelligent Solar Tracking Control System Implemented in an FPGA Portable Telemedicine Monitoring Equipment Develop Embedded Systems with Altera FPGAs (PDF) From a "First-Time Designer's Guide" to "Verification and Board Bring-Up", the design guides that make up this handbook explain the best practices for developing embedded systems with Altera. If you're new to Altera's embedded products, the design guides will bring you up to speed quickly. Experienced users will learn how to improve efficiency and reduce design cycles. See how it can help you with your next design. "Reduce Power by Adding Hardware Accelerators," Embedded.com The rule of thumb in embedded system design has been that adding hardware increases power demands. The careful use of hardware accelerators, however, inverts the rule: adding hardware can reduce power. Download the article and see for yourself. App Note: Implementing an LCD Controller (PDF) This new application note shows how to create your own LCD module embedded design. The example used is based on the Nios II Embedded Evaluation Kit and includes background information on the LCD subsystem and porting guidelines. Download today. Webcasts & Training Training: New System-on-Chip Designer Curriculum Need to embed a soft-core processor in your FPGA? Learn how with the SoC Designer Curriculum. This course-by-course curriculum lists every class you need to become an expert SoC designer, including integrating processors and software on a Nios II Development Kit. Altera also offers instructor-led training in locations around the US: Designing with the Nios II Processor and SOPC Builder Developing Software for the Nios II Processor

	To ensure that you receive future issues of Inside Edge, please add announcements@altera.com to your address book. As a subscriber to the Inside Edge enewsletter, you will receive a monthly email newsletter. Altera respects your privacy. If you no longer wish to receive this enewsletter, please unsubscribe. Subscribe to additional Altera email updates and enewsletters, or view/edit all of your Altera email subscriptions. Altera email communications include: Product Announcements & Updates Code:DSP enewsletter Embedded enewsletter Webcast enewsletter Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation

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Copyright © 1995-2006 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA

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Altera MAX IIZ CPLDs Win Mobile Gold in Beijing

announcements@altera.com (Altera DSP eNewsletter) — Tue, 24 Jun 2008 16:08:00 GMT

Altera MAX IIZ CPLDs Win Mobile Gold in Beijing

San Jose, June 23, 2008—Altera Corporation (NASDAQ: ALTR) announced today that Shenzhen Huayu Communications Technology Company Limited has selected MAX^® IIZ CPLDs for use in its new P1200 portable handsets. Chosen for their ability to quickly and securely implement new features and capabilities while consuming minimal power and board space, Altera’s MAX IIZ CPLDs manage several peripherals in the P1200 handsets, including a Radio Frequency Identification (RFID) reader, an Infrared Data Association (IRDA) sensor, a Bluetooth interface, and LED control. The P1200 handsets made their debut during the Hangzhou public transportation system’s bicycle project in May 2008, and in August, they will be used for ID identification, logistics, and public transportation services for the Beijing Summer Games.

“With the 2008 Olympics rapidly approaching, we were challenged with getting our handsets to market quickly with unique features that are not supported by off-the-shelf components,” said Wang Shao Wei, vice president of engineering at Shenzhen Huayu Communications Technology Company Limited. “Participating in the MAX IIZ early access program enabled us to leverage Altera’s first zero-power CPLDs as soon as they were released, and to meet our aggressive schedule with a cost-effective solution that minimizes our power consumption and increases design security.”

Leading-edge handset developers such as Huayu face the challenge of quickly adding new product features demanded by their customers. The lengthy development cycles of full-custom ASICs and the lack of flexibility of ASSPs have limited developers’ ability to meet this challenge. In addition, features based on off-the-shelf components like ASSPs are easily duplicated by other manufacturers, severely reducing the benefits that handset developers enjoy when they deliver first-to-market capabilities.The MAX IIZ family addresses these concerns by delivering the lowest power consumption of any CPLD in the market, the highest amount of user-customizable logic resources per board area and design security.

“As the world’s leading provider of CPLDs, Altera has a long history of reliably delivering custom logic products that enable product innovation,” said Luanne Schirrmeister, director of marketing, low-cost products, Altera Corporation. “Huayu’s P1200 is a great example of how forward-looking innovators in the portable handset industry are using MAX IIZ CPLDs to deliver differentiating features as soon as the market demands them.”

About MAX IIZ CPLDs

MAX IIZ devices are available in densities of 240 and 570 logic elements (LEs), with ultra-small MBGA packages as small as 5x5 mm, and as many as 160 I/Os. Their look-up table (LUT)-based architecture offers increased logic density and I/O count, thus allowing greater integration of functions and substantially reducing board space and power consumption while lowering overall system costs. The advanced features and capabilities of MAX IIZ CPLDs—such as user flash memory, an internal oscillator, cost optimization, high logic density, smaller packages and low power consumption—far surpass those of all traditional macrocell-based CPLDs.

For more information on MAX IIZ devices, visit www.altera.com/maxiiz. For more information on MAX IIZ devices in portable applications, visit www.altera.com/b/maxiiz-portable.html.

About Altera

Altera^® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.

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Introducing 40-nm Stratix IV FPGAs and HardCopy IV ASICs

announcements@altera.com (Altera) — Mon, 19 May 2008 18:31:00 GMT

Introducing 40-nm Stratix IV FPGAs and HardCopy IV ASICs

Introducing 40-nm Stratix IV FPGAs and HardCopy IV ASICs

Learn About Altera's 40-nm Portfolio

Altera introduces its new 40-nm portfolio, featuring Stratix^® IV FPGAs and HardCopy^® IV ASICs. With these new device families and the Quartus^® II software v8.0, you don't need to choose one benefit over another. You get:

The highest density AND the lowest power
The benefits of FPGAs AND the benefits of ASICs
Software with the highest logic utilization AND the fastest compile times
Cutting-edge 40-nm technology AND a low-risk path to production

Altera's 40-nm portfolio delivers new levels of system-on-a-chip integration, so you can think AND, not OR.

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